Classes are subject to change at any time. Any course may be withdrawn from the current listing if the enrollment is too small to justify conducting the course or as a result of a reduction in funding.
EE 210 | Intro to Elec Engineering Hours: 3 |
001 | 80429 | T 4:00p-6:45p Location: SCIT 214 Laddomada, Massimiliano | 24 | 8 | |
| Meets 8/25/2011 – 12/15/2011 Vita Syllabus Books/MaterialsInstructors Permission Corequisites C: PHYS 2326 PHYS 2126 Corequisites S: PHYS 2326 PHYS 2126 Prerequisites: (Lvl UG MATH 2313 Min Grade D or Lvl UG MATH 2413 Min Grade D) Campus: Main Campus (Texarkana, TX) Instructional Method: FACE | |
EE 320 | Circuit Laboratory Hours: 1 |
001 | 80030 | W 4:00p-6:45p Location: SCIT 214 Laddomada, Massimiliano | 24 | 5 | |
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EE 332 | C++ Programming Hours: 4 |
001 | 80026 | F 2:00p-5:40p Location: SCIT 215 Govindaswamy, Victor | 24 | 2 | |
| Meets 8/25/2011 – 12/15/2011 Vita Syllabus Books/MaterialsPrerequisites: Lvl UG CS 1315 Min Grade D Campus: Main Campus (Texarkana, TX) Instructional Method: FACE | |
EE 335 | Electronics Hours: 3 |
001 | 80031 | R 4:00p-6:45p Location: SCIT 214 Lala, Parag | 24 | 7 | |
| Meets 8/25/2011 – 12/15/2011 Vita Syllabus Books/MaterialsPrerequisites: Lvl UG EE 210 Min Grade D Campus: Main Campus (Texarkana, TX) Instructional Method: FACE | |
EE 340 | Computer Architecture Hours: 3 |
001 | 80027 | W 1:00p-3:45p Location: SCIT 213 Vainstein, Feodor | 24 | 4 | |
| Meets 8/25/2011 – 12/15/2011 Vita Syllabus Books/MaterialsPrerequisites: Lvl UG CIS 320 Min Grade D or Lvl UG EE 321 Min Grade D Campus: Main Campus (Texarkana, TX) Instructional Method: FACE | |
EE 390 | Ethics in Technology Hours: 3 |
001 | 80028 | M 4:00p-6:45p Location: SCIT 213 Lala, Parag | 24 | 8 | |
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EE 425 | Signals and Systems II Hours: 3 |
001 | 80032 | M 1:00p-3:45p Location: SCIT 214 Laddomada, Massimiliano | 24 | 4 | |
| Meets 8/25/2011 – 12/15/2011 Vita Syllabus Books/MaterialsPrerequisites: Lvl UG EE 325 Min Grade D Campus: Main Campus (Texarkana, TX) Instructional Method: FACE | |
EE 470 | Digital Design Using VHDL Hours: 3 |
001 | 80033 | T 1:00p-3:45p Location: SCIT 214 Lala, Parag | 24 | 10 | |
| Meets 8/25/2011 – 12/15/2011 Vita Syllabus Books/MaterialsPrerequisites: Lvl UG CS 320 Min Grade D or Lvl UG EE 321 Min Grade D Campus: Main Campus (Texarkana, TX) Instructional Method: FACE | |